Negative Clamping Circuit: How Does Large Time Constant Affect Output Waveform?

hey, i just wish to clarify the working principles of a clamping circuit.......
Negative Clamping Circuit:-
1. Like when the capacitor is charged in the first half cycle of the
input signal(wudnt it take long time as the time constant of the capacitor used is large?)
2. how does the sinusoidal waveform of the input signal retain itself when the voltage of the
capacitor(which acts as the supplier of voltage) becomes constant,after getting charged (due to large time constant)?
3. what do we mean when we say that clamping circuits shift the dc level of the input signal?

1) An ideal diode doesn't have any impedance, so the time constant is low and the capacitor charges almost instantaneously. For a very large capacitor and non-ideal voltage sources and diodes it will take several cycles to equilibrate. For ideal components it happens instantaneously.
2) Once the capacitor is charged it can't discharge, so it has a constant voltage across it. If we call the capacitor voltage vcap (this is constant), the output voltage is vout = vin + vcap. So if vin is sinusoidal, so is vout (with an additional dc term, vcap).
3) The dc level of a signal is the average value (for a sinusoidal signal this is the midline). The dc level of the signal is changed by vcap (see equation above).

thank you.....

*sorry for interrupting…*
my question is how about to design an ac current meter/analyzer?
it is as what an clamp meter is about…i want to analyze the current in the DB and the data receive will be deliver into microcontroller..

_i'm new and dont know much about this topic_