Relative Propagation Delays for CMOS Inverter, NAND, NOR, XOR, AOI Gates?

Can anybody give me RELATIVE gate delay info for the basic CMOS digital logic circuits: Inverter, Nand, Nor, Xor, maybe AOI? I used to know this stuff for the dinosaur days of Schottky TTL, and there were big propagation differences between Nand and Xor, for example.

I'm not worried about fanout, trace length, or other parasites, just want to be able to do some back-of-envelope calculations for some SoC logic I'm looking to design (relative static memory delay would be a bonus!).

Online I've found lots of formulas, which I don't need, and some circuit diagrams, which are interesting in that it seems like with CMOS, the circuits for all of the logic I mentioned in the first paragraph LOOK as though any relevant transistors fire in parallel, which would imply that the delays for all the different gates should be about the same. Am I right or wrong about this?

You can get that from the datasheets. Look under "AC Electrical Characteristics" [Fairchild] or "Dynamic Electrical Characteristics" [TI] or just look for "Propagation Delay" in the datasheet. Look up each logic device and draw your own conclusions.

Well, we're getting closer. I should have mentioned that I did try the datasheet route. Turns out I ended up at a crappy datasheet site where every search turned up a different manufacturer and logic family. Was like comparing apples to oranges to pomegranates - not helpful at all.

However, inspired by your reply, I focused in on one specific type: the Fairchild 74VHCXX family. Much better. All the basic 2-input gates do indeed have very similar delays. The XOR is about 1.33 longer, not surprising since four transistors are switching in series while the other gates switch two.

So I am more confident than before, yet I still would like to see an answer pertaining to internal system-on-chip / ASIC / standard cell technology rather than discrete logic. Anyone?

Also, Fairchild has discontinued the AOI gate & memory cell ICs in that family, or perhaps never made them in the first place, which leaves me with semi-educated guessing for those logic subsystems.

But at least I'm now 70% - 80% confident in my knowledge, which is an upgrade from 0%. So, thanks.

Well, your propagation delay depends on a bunch of things.

Since it is CMOS, your capacitances are going to play a role in how quickly the output can change. That said, the more transistors used in making the specific gate, the longer of a propagation delay.

To answer your final question, just because they are parallel, doesn't mean the delays are the same. The physical layout of the transistors, to implement the function, will affect it.

Sadly, there are too many variables involved in order to give you a relative value.

No, actually I'm getting close to the info I want. At this point I don't care about ratios of say, 1.1 : 1 between two different kinds of gates, while if I ran into a 2 : 1 ratio, I'd think, "Whoa, I'd better try to avoid those slow gate types in my critical path logic." Like I first wrote, 'back-of-envelope calculations' are just fine for me at this time.

Maybe you can answer another quick question for me ... is the 6-transistor SRAM cell still the basic one in use?

Thanks.