Counter in VHDL

Can you please just review my following counter with respect to state table because i doubt of its VHDL code logic. Please help me to correct if you found any error.

C D Q QN
1 0 0 1
1 1 1 0
0 X last Q last QN


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_counter is
port (
coutQ :out std_logic_vector (1 downto 0); -- Q Output of the counter
coutQN :out std_logic_vector (1 downto 0); -- QN Output of the counter
enable :in std_logic; -- Enable counting
clk :in std_logic; -- Input clock
reset :in std_logic -- Input reset
);
end entity;

architecture rtl of up_counter is
signal count :std_logic_vector (1 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
count '0');
elsif (rising_edge(clk)) then
if (enable = '1') then
count