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74LS92 Divide by 12 Counter Not Counting, Outputs Random—Wiring or Pin Setup Issue?

15 13
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  • #1 21682339
    david lopez
    Anonymous  
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  • #2 21682340
    David Ashton
    Anonymous  
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  • #3 21682341
    Chip Fryer
    Anonymous  
  • #4 21682342
    david lopez
    Anonymous  
  • #5 21682343
    John Beetem
    Anonymous  
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  • #6 21682344
    PeterTraneus Anderson
    Anonymous  
  • #7 21682345
    david lopez
    Anonymous  
  • #8 21682346
    david lopez
    Anonymous  
  • #9 21682347
    David Ashton
    Anonymous  
  • #10 21682348
    PeterTraneus Anderson
    Anonymous  
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  • #11 21682349
    David Ashton
    Anonymous  
  • #12 21682350
    PeterTraneus Anderson
    Anonymous  
  • #13 21682351
    PeterTraneus Anderson
    Anonymous  
  • #14 21682352
    David Ashton
    Anonymous  

Topic summary

The discussion addresses issues with the 74LS92 divide-by-12 counter not counting correctly and producing random outputs. Key points include correct pin wiring: Vcc (5V) on pin 5, GND on pin 10, MR1/2 inputs (pins 6/7) tied low, Q0 (pin 12) connected to CP1 (pin 1), and clock pulses fed into /CP0 (pin 14). Using a jumper wire connected directly to the positive terminal as a clock source causes switch bounce, resulting in multiple unintended clock pulses and erratic counting. Clean clock pulses with fast rising and falling edges are essential; a 555 timer in astable mode or a debounced switch circuit using NAND gates (e.g., 74LS00) is recommended. Capacitors can provide debounce delay but do not produce the sharp edges required by the 74LS92 clock inputs, which trigger on the falling edge. Schmitt-trigger gates like 74LS132 or 74LS14 can convert slow input transitions into fast edges. Alternative solutions include using a 74LS123 retriggerable monostable multivibrator for pulse shaping. Proper power supply decoupling with electrolytic and ceramic capacitors near the IC is advised to ensure stable operation.
Summary generated by the language model.
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