Why Does 74HCT393 Not Count When Reset Pin Is Driven by EEPROM DQ0 Output?

Hello, everyone. I have a 2-chip schematic (attached) that is giving me problems. If the brown wire is connected to the EEPROM's output pin DQ0, as it is in the schematic attached, the 74HCT393 doesn't count, as if it's being constantly reset. However, if I simply move the wire so that it's connected to ground instead of the EEPROM, the counter counts just fine.


I have checked the voltage coming out of the EEPROM at each count, and the voltages match what they should be. For this circuit, the EEPROM should reset the counter when the counter reaches 3, and it does exactly that. If the counter is 3, the EEPROM outputs 4.8V at DQ0; if the counter is anything else, the EEPROM outputs 0V. I should note that I can only do this testing if the brown wire is grounded (not connected to the EEPROM) because the counter doesn't count when connected to the EEPROM, but I have verified that DQ0 is at 0V when the brown wire is connected between the 2 chips and the counter is reset (at 0).



This circuit is the smallest circuit I have been able to make to reproduce the problem. It is based on a much larger circuit that I have built twice, both times with significantly more and longer wires than in this small circuit. All 3 circuits have had the exact same issue.


I have tried using different 74HCT393 and EEPROM chips (2 of each), but they behave the same. I have used the EEPROM in other circuits successfully. I have also simulated the logic in LogicWorks and Digital Works.



I appreciate any help that can be given!


PS: I don't have the counter connected to A3-A0 on the EEPROM because it isn't connected there in the full circuit. I was too lazy to write a new program to reprogram this EEPROM just for this simple circuit.

Hi Christopher-The first thing that jumps out at me is the absence of bypass capacitors in your circuit. I have seen really screwy things happen when you get some noise on the supply lines.  Try adding a couple ceramic capacitors, maybe around .1uF, as close to  Vcc and Gnd (Vss and Vdd) as possible. It is important to keep those wires short.  Use ceramic capacitors if possible.  It's important that the capacitors have a low ESR (equivalent series resistance).  In a pinch you may be able to use film capacitors if you don't haver ceramic capacitors available.If that doesn't help, try adding another ceramic capacitor, just a few picofarads, between 1MR and GND.  My thinking here is that you may be getting some glitches out of the EEProm as the counter counts.Another possibility is to make sure that A3-A0 are not floating since you mention that they are not connected to the counter. I'll be eager to hear if this helps.-Rick 

Christopher,Rick's comments caused me to check the data sheet for the 74HCT393. The 74HTC393 is a ripple counter. This means that the outputs do NOT all change at the same time. So it's likely that you will have glitches on the address lines to the EEPROM which can lead to glitches on the output lines.Check your EEPROM output for glitches with an oscilloscope if you can.

I agree with Rick's observations, and I have an observation of my own.The 74HCT393 MR input is asynchronous, so any narrow high pulse will reset the counter. When the counter counts, the EEPROM address changes. I suspect the EEPROM output pulses high while the EEPROM's access time elapses.Replace the 74HCT393 with a 74HCT163. The 74HCT163 is fully synchronous, so all inputs are read only on the rising edge of the clock. The '163 will ignore the EEPROM output pulses, as the pulses occur only between clock pulses. The '163 has an active-low reset, so you will have to re-program your EEPROM. Also, tie the remaining '163 inputs (other than resetn and clk) high. I have had a love affair with the fully-synchronous '163 ever since I found the 74163 in the 1972 Signetics catalog.

Even though Elizabeth is correct, let’s assume that the counter’s outputs change at exactly the same time, you still have the access time of the EPROM as the decoded address settles. I’ll bet that your EPROM does not have all the bits set to 0, so as each transient address accesses some cell there is a transient high in the reset line causing the counter to reset.
Depending on the clock pulse length vis-a-vis the settling time of the counter and the access time of the EPROM a solution might be to place a pull down resistor to ground on the reset input and connect the clock pulse to the !OE of the EPROM. In my day the access time of the EPROM was at its fastest 350nS, so I reckon it must be at about 150nS now. Data sheets will have the data.The pulses can be very short, but a ‘scope would be helpful

You guys rock! I am happy to say that the 2-chip board is now fully working (the counter now counts and resets at 3). Nobody's ideas worked individually, but I combined them to create my own idea that worked. The circuit that worked is below.
How I came up with the circuit: You guys had mentioned glitches, which were things I hadn't considered but made complete sense in my head. This is especially true because erasing the EEPROM fills all the addresses with 0xFF, not 0x00. I tried ceramic capacitors in various places (Rick, I appreciate you giving me specific sizes to try), but none of them worked. Then I went into PSpice and came up with the above circuit to give capacitance to the 1MR input of the counter.
I now have 2 related questions.1) In the design phase of a project, how would I know if a signal needs a circuit such as the one pictured above to account for glitches? Elizabeth mentioned "ripple counter" means that not all the outputs change at the same time, which I didn't know. Should I just put a similar circuit anywhere the signal is going to an asynchronous input that can't handle glitches?2) How would I pick a resistor and capacitor size? I used 1kΩ and 1nF because that means tau=time constant=1us, which is significantly longer than the EEPROM's 70ns read access time. However, what's to stop me from using 100Ω and 10nF for the same tau? How do I even pick a tau?
I will test the large circuit with this new reset signal/circuit tomorrow. It's currently 3:30am. I'm just happy the 2-chip board is now working and I know why.

If you want to cascade multiple 74HCT163's to get larger counters, here is information from the 1972 Signetics datasheet that is not in the modern datasheets I've seen. Your clock goes to the clock inputs on all the 74HCT163's. The first 74HCT163 has its Ep and Et inputs tied high, and its RC output goes to the Ep inputs  on all the other 74HCT163's and to the Et input of the second 74HCT163. The RC output of the second 74HCT 163 goes to the Et input of the third 74HCT163. The RC output of the third 74HCT163 goes to the Et input of the fourth 74HCT163. And so on.Your clock period must be longer than the 74HCT163 output propagation delay plus the EEPROM access time plus the 74HCT163 input setup time.If you can stand using a clock of half this speed, so the propagation times are less than half the clock period, you can fix your problem with a 74HCT74 flipflop inserted in the brown wire. The EEPROM output drives the 74HCT74 D input. The 74HCT74 Q output drives the 74HCT393 MR input. Connect the flipflop clock input to the clock pulse that drives the 74HCT393 clock input. Be sure to connect all unused 74HCT inputs to Vdd or GND. The 74HCT393 clocks on the falling edge of the clock pulse, while the 74HCT74 clocks on the rising edge of the clock pulse, so the 74HCT74 Q output changes state midway between 74HCT393 clock events. This eliminates race conditions.If you use 74HCT163 counters and also feed all the EEPROM outputs through D flipflops (these flipflops are called a register), you eliminate all glitch pulses and you are building a simple fully-synchronous finite state machine, the basis of building  a CPU. With registered EEPROM outputs, you could use some of the EEPROM outputs for your counter and eliminate the 74HCT393 entirely. You can use a 74HCT163 as a four-bit register.
Aubrey's suggestion of connecting the clock pulse to !OE of the EEPROM will not work because the 74HCT393 clocks on the falling edge of the clock. Connecting the clock pulse to !OE and through an inverter to the 74HCT393 clock, should work.I suspect your EEPROM outputs would pulse high even if all the bits were programmed 0. When the address changes, the old memory cell is likely deselected before the new cell is selected, so there is a short time when no cell is selected. Traditionally forty years ago, the no-cell-selected state was high.I recommend you get some 74HCT163's and start learning fully-synchronous logic design.

A correction: When cascading multiple 74HCT163's, the Et input of the second 74HCT163 should be tied high by connecting Et to Vdd. The RC-output Et-input series chain performs the ripple-carry function through the entire cascade of 74HCT163's, as Et is gated into RC inside each 74HCT163. Ep is not gated into RC, so does not affect the ripple-carry propagation. Connecting the first RC to all the later Ep's gives the ripple-carry fifteen clocks to propagate before the later 74HCT163's are next count-enabled by the first RC connected to Ep.

In addition to my previous comment about the 2-chip board working, I have now verified the full circuit works with the RC circuit fix for 1MR. I am still wondering about the questions I asked in that previous comment, though.