perhaps you could use one that has more than one "circuit" per chip, then you can parallel them to reduce the affect of wiper resistance. E.g. six 100K pots in parallel, for a 16.7K pot, or six 50K for 8.3K, etc. For a 70 ohm wiper resistance, that will be an effective Rw of around 11.7 ohms. Still not in the single digits but on the way ;)
Also, these are typically CMOS devices, so the higher the supply voltage, the lower the "wiper resistance". Also, check out the "Wiper vs Voltage" diagrams. That should allow you to select an 'active' region for optimally low Rw. For instance, the AD5206 has an Rw around 43 - 45 ohms with a VDD of 5.5V and a Common Mode voltage in the range of 0 to 3.5 volts. Divide that by 6 and you get something more like 7.5 ohm wiper resistance (though the specs say that Rw can go as high as 100 ohms at VDD = 5V, but that probably takes into consideration the full temperature range, as I doubt Rw is temperature compensated, or perhaps they are lumping in the MIN VDD specs in that number).
Also, the AD5206's Absolute MAX VDD to GND is 7 volts, so consider running it at higher than 5V to get the lowest possible Rw. Probably good to add extra filtering on the supply line so spikes don't violate the MAX voltage.
In matters such as this, you can always contact the manufacturer and ask for recommendations. I've done this (even by email) and received all kinds of very useful information (including things I had never even considered)
