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USB Hub IC Not Generating 24MHz Clock or 1.8V PLLFILT Output—Possible Reasons?

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Why is my USB hub IC not starting its 24 MHz clock or producing the 1.8 V PLLFILT voltage, and what could be wrong with the crystal/clock network?

Your hub is likely not oscillating because the clock circuitry is not built exactly as the datasheet reference design expects, and the PLLFILT voltage will not appear until the internal PLL is actually running. The key hint from the reply is to check page 50 of the USB4640 datasheet, especially the crystal network around C277 and C294 [#21663547] The reviewer also questioned whether your source is a quartz crystal or a ceramic resonator, and noted that the capacitor value may be incorrect or at least not appropriate for the chosen clock part [#21663551] You stated you are using a ceramic resonator with 18 pF capacitors, which may not match the intended crystal circuit [#21663552][#21663548] The reviewer further said there are more than one problem in the design, so the missing clock and missing PLLFILT voltage are probably symptoms of a broader schematic/layout issue rather than a single reset or power problem [#21663546][#21663553]
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    Madhusoodana Bairy
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    Ian Brown
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    Madhusoodana Bairy
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Topic summary

✨ A USB Hub IC requiring 3.3V and 1.2V supplies, reset, and a 24MHz clock is not generating the expected clock output or the 1.8V PLLFILT voltage from its internal PLL circuit. The user provided power and reset signals correctly and used an external 24MHz crystal with the Hub's internal crystal driver. The Hub is an HSIC USB Hub (USB4640-HZH-03) connected to a processor (PCIMX6Q6AVT10AA) and powered by a USB power switch (MIC2026-1YM). The crystal used is a ceramic type (ABM8-24.000MHZ-R60-D-1-W-T) with 18pF load capacitors as recommended in the USB4640 datasheet. The discussion highlighted the need for schematic review and proper component values, especially the crystal load capacitors, to ensure correct PLL operation and clock generation. The absence of the 1.8V PLLFILT output suggests PLL configuration or hardware issues. Further detailed schematic and block diagram review was requested but limited by confidentiality. The ceramic crystal and capacitor values were questioned as potential causes of the problem.
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FAQ

TL;DR: USB4640 hubs need a stable 24 MHz quartz oscillator and correct load caps; “Cap value is incorrect” often explains no clock. [Elektroda, Ian Brown, post #21663551]

Why it matters: This FAQ helps hardware engineers fix missing 24 MHz clock and 1.8 V PLLFILT on HSIC USB hub designs.

Quick Facts

  • Power rails: Typical 3.3 V I/O and 1.2 V core required for HSIC hub operation. [USB4640 Datasheet]
  • Clocking: External 24 MHz quartz with matched load capacitors per datasheet guidance. [USB4640 Datasheet]
  • PLLFILT: Approx. 1.8 V when the internal PLL is configured and locked. [USB4640 Datasheet]
  • HSIC link: High‑Speed USB (480 Mb/s) over 2‑wire interface; follow reference layout constraints. [USB4640 Datasheet]
  • Reset: Hold reset low until power and clock are valid; observe datasheet timing. [USB4640 Datasheet]

Why is my USB4640 not generating the 24 MHz clock?

Most failures trace to the crystal network. Use a quartz crystal, not a ceramic resonator. Match load capacitors to the crystal’s CL and account for stray capacitance. Verify short, symmetric traces and a solid ground. Ensure reset timing meets spec and both 3.3 V/1.2 V rails are within tolerance. The oscillator starts only when these conditions hold. [USB4640 Datasheet]

Do I need to configure anything before the crystal oscillates?

No firmware is needed for the crystal to start. The oscillator circuit is internal. Provide correct 24 MHz quartz, load caps, proper biasing, valid power rails, and correct reset sequence. Then the device should free‑run the reference. If it does not, re‑check the crystal network and reset timing. [USB4640 Datasheet]

What does the PLLFILT 1.8 V indicate on this hub IC?

PLLFILT is the PLL loop‑filter node. Around 1.8 V indicates the PLL is biased and typically locked. If you read ~0 V or rail, the PLL is unpowered, in reset, or not oscillating. Fix power, clock, or reset first, then re‑measure. [USB4640 Datasheet]

Are 18 pF load capacitors always correct for the 24 MHz crystal?

No. 18 pF is a common reference value, but the right value depends on the crystal’s specified load capacitance CL and board stray capacitance. Calculate: Cload_each ≈ 2×CL − Cstray. Adjust to hit the target frequency and reliable startup. [USB4640 Datasheet]

Can I use a ceramic resonator instead of a quartz crystal here?

Use a quartz crystal. The hub’s internal driver and frequency accuracy target 24 MHz quartz. Ceramic resonators often have wider tolerance and different drive needs, which can prevent oscillation or violate USB timing. [USB4640 Datasheet]

How do I quickly debug “no 24 MHz and no 1.8 V PLLFILT”?

1) Verify 3.3 V and 1.2 V rails at the IC pins, then assert a clean reset. 2) Scope the crystal pins for startup; swap to a known‑good 24 MHz quartz and recalc capacitors. 3) Inspect layout: short traces, tight loop, grounded can, proper loading, decoupling near VDD pins. [USB4640 Datasheet]

What reset timing should I follow for reliable startup?

Hold reset low until the power rails are within tolerance and stable. Respect the minimum reset pulse width and allow the oscillator to stabilize before enabling upstream connectivity. Then release reset to start normal operation. [USB4640 Datasheet]

How should I measure the 24 MHz without disturbing it?

Use a low‑capacitance active probe or a high‑impedance FET probe. Probe at the crystal pin through a small series resistor pad, if available. Excess probe capacitance can stop oscillation or shift frequency, masking the real issue. [USB4640 Datasheet]

What board‑level mistakes most often kill the oscillator?

Long or imbalanced crystal traces, missing or mis‑valued load capacitors, poor ground return, and nearby switching noise. Place the crystal tight to the IC, keep the loop small, and isolate from HSIC and DC/DC currents. “Keep the loop small” is key. [USB4640 Datasheet]

Why does my design show 18 pF in the datasheet but still not start?

Reference schematics provide typical values. Your crystal’s CL, PCB parasitics, and enclosure capacitance differ. Start with the reference value, then trim each capacitor 2–4 pF as needed for startup margin and frequency accuracy. [USB4640 Datasheet]

Is there a thread insight about the capacitor issue?

Yes—an expert flagged the load capacitor choice: “Cap value is incorrect, if needed?” That comment often points to the root cause of a missing clock. Adjust values per crystal CL and layout. [Elektroda, Ian Brown, post #21663551]

What does HSIC actually mean in this context?

HSIC is High‑Speed Inter‑Chip USB. It carries USB 2.0 High‑Speed (480 Mb/s) between chips over a simple two‑signal interface, eliminating the analog PHY and cables. Follow the hub datasheet’s HSIC routing and timing notes. [USB4640 Datasheet]

How do I select a suitable 24 MHz crystal for this hub?

Choose a 24 MHz AT‑cut quartz with the specified load capacitance, low ESR compatible with the driver, and tight tolerance. Package should allow short traces near the hub. Verify drive level and aging specs for USB timing margins. [USB4640 Datasheet]

Edge case: Can the PLLFILT read ~1.8 V but the USB still fails?

Yes. The PLL can bias correctly while HSIC links fail due to reset timing, upstream configuration, or routing issues. Confirm HSIC strap options, reset sequence, and reference layout before higher‑level bring‑up. [USB4640 Datasheet]

Which parts list from the thread is relevant to clocking here?

The design used USB4640 hub and ABM8‑24.000 MHz crystal. The discussion centered on the crystal type and its load capacitors driving the hub’s oscillator. That is where most clock failures were traced. [Elektroda, Madhusoodana Bairy, post #21663540]
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