Removing latches generated from missing assignment in if statement

I have written an if else statement in *VHDL*, wherein one signal is used in if statement and not in else statement, which has resulted into latch. This should not happen. One way to remove this is assign signal values in both cases, which is not possible for my logic. What I am doing is similar to...

if(c>0) then
a='1';
else
b='1';
end if;

Now latches are generated for a and b signals. What are the different ways to avoid latch formation?

I cannot do like

if(c>0) then
a='1';
b='0';----I dont want b to be 0 here
else
b='1';
a='0';----same here
end if;

Have a and b take a default value ... otherwise simply refreshing the value before the if statement will still generate latches. If the outputs a and b are outputted to a flip-flop (which I believe to be true otherwise you will need latches to latch the a and b values) you can do the following:

process (clk, reset_n) begin
if rising_edge(clk) begin
if (reset_n = '0') begin
a_ff