postive edge triggered D flipflop

In the above circuit if clock(CLK 1) goes from 0 to 1 and input D =0 ,this makes Q=0.
It is stated that when the clock is at HIGH(1) any further change in input does not affect output,how it is so .Can you explain me please.Thank you in advance

Hi Bhuvanesh,

I have here link on:
* Edge-triggered Flip-Flop,State Table, State Diagram
* Positive Edge-Triggered D Flip-Flop Analysis
* Edge-triggered latches: Flip-Flops.

Hope it Helps

Hi Bhuvanesh,

When a D flip flop is positive edge triggered, its output changes similarly with the input if the clock changes from a 0 to 1. From what you said, since D is 0 at the time the clock changes from 0 to 1, Q becomes 0. If the clock is at HIGH all the time, it would not affect the output since it did not detect a 0 to 1 change in the clock. It is only when the clock changes from a LOW to HIGH that the output state follows the input state.

Please see the image attached for additional reference. Observe how Q changes with respect to the CLOCK and D.