One more solution came to my mind but probably too risky.
I am using an ESP32-V3-02 with an internal PSRAM. The memory is powered from the ESP pin. It is, admittedly, labelled "Output power supply". However, I think this is a regular IO pin. It is externally accessible. So potentially VDD could be connected to it. In this situation, a low state on EN will not disable the PSRAM power supply and the data in memory will remain