Does the low state of the EN pin internally disable the power supply to the RTC module in the EPS32 ?

Yes, when the state on EN (CHIP_PU) is low, the internal low voltage regulator 1V1 which also powers the RTC domain is switched off. When the high state on CHIP_PU is restored, an ESP reset is performed.

Is it possible to somehow preserve the time between resets triggered by the low state of the EN pin ?

Generally, this should not allow low states on the EN - it should be pulled up to the power supply. Data can be stored in flash memory (NVS).

On the device I have a hardware watchdog connected to the EN pin. If for some reason it triggers then I lose the timing information completely. I wonder if I should go along with this. Frequent NVS memory writes are unlikely to be a good solution

Depending on the flash memory used in the ESP32, this could be between 100,000 and 1 million writes.

One more solution came to my mind but probably too risky. I am using an ESP32-V3-02 with an internal PSRAM. The memory is powered from the ESP pin. It is, admittedly, labelled Output power supply. However, I think this is a regular IO pin. It is externally accessible. So potentially VDD could be connected to it. In this situation, a low state on EN will not disable the PSRAM power supply and the data in memory will remain

The PSRAM is powered internally from the VDD_SDIO domain, as is the flash. The VDD_SDIO regulator is also switched off when a low state is applied to EN. . Connecting an external 3V3 to VDD_SDIO will automatically disable the internal VDD_SDIO controller. Sleep functions will then cease to function properly.

Does a low state pin disable power to the RTC module in the EPS32?

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#1 20082643 30 Jun 2022 18:44

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20082643 30 Jun 2022 18:44

Does the low state of the EN pin internally disable the power supply to the RTC module in the EPS32 ?
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#2 20082891 30 Jun 2022 21:29

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20082891 30 Jun 2022 21:29

Yes, when the state on EN (CHIP_PU) is low, the internal low voltage regulator 1V1 which also powers the RTC domain is switched off. When the high state on CHIP_PU is restored, an ESP reset is performed.
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#3 20082908 30 Jun 2022 21:41

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20082908 30 Jun 2022 21:41

Is it possible to somehow preserve the time between resets triggered by the low state of the EN pin ?
#4 20082915 30 Jun 2022 21:45

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20082915 30 Jun 2022 21:45

Generally, this should not allow low states on the EN - it should be pulled up to the power supply. Data can be stored in flash memory (NVS).
#5 20082939 30 Jun 2022 21:55

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20082939 30 Jun 2022 21:55

On the device I have a hardware watchdog connected to the EN pin. If for some reason it triggers then I lose the timing information completely. I wonder if I should go along with this. Frequent NVS memory writes are unlikely to be a good solution
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#6 20082945 30 Jun 2022 21:59

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20082945 30 Jun 2022 21:59

Depending on the flash memory used in the ESP32, this could be between 100,000 and 1 million writes.
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#7 20083206 01 Jul 2022 07:06

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20083206 01 Jul 2022 07:06

One more solution came to my mind but probably too risky.
I am using an ESP32-V3-02 with an internal PSRAM. The memory is powered from the ESP pin. It is, admittedly, labelled "Output power supply". However, I think this is a regular IO pin. It is externally accessible. So potentially VDD could be connected to it. In this situation, a low state on EN will not disable the PSRAM power supply and the data in memory will remain
#8 20083929 01 Jul 2022 16:37

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20083929 01 Jul 2022 16:37

The PSRAM is powered internally from the VDD_SDIO domain, as is the flash. The VDD_SDIO regulator is also switched off when a low state is applied to EN.

.

Connecting an external 3V3 to VDD_SDIO will automatically disable the internal VDD_SDIO controller. Sleep functions will then cease to function properly.
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Topic summary

When the EN (CHIP_PU) pin of the ESP32 is set to a low state, it disables the internal low voltage regulator that powers the RTC module, resulting in a loss of timekeeping. To preserve time between resets, users can store data in flash memory (NVS), although frequent writes may not be ideal due to limited write cycles (100,000 to 1 million). Some users consider alternative solutions, such as connecting external power to the PSRAM, but this risks disabling sleep functions and may not maintain data integrity during power loss.
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Does a low state pin disable power to the RTC module in the EPS32?

Does a low state pin disable power to the RTC module in the EPS32?

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