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Computer on Z80 with VGA by piotr_go

piotr_go  18 18486 Cool? (+66)
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TL;DR

  • A modular Z80 computer combines a motherboard with an IO + board for VGA output, keyboard input, sound, SD-card access, and clock generation.
  • The motherboard carries a Z80, 512kB RAM, 512kB flash, an 8255 I/O chip, and an ATF1502AS 5V CPLD that also handles bank switching.
  • Si5351 generates the VGA, UARTa, and YMZ284 clocks, while the IO board uses an XC9572XL, GD32, and DS1302Z for UART/SPI control, image generation, and timekeeping.
  • The build supports CP/M and ZSDOS and runs from a 5V power supply through USB-C.
  • The earlier version used a Xilinx CPLD and needed an extra 3.3V->5V level converter.
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It was already 8051, now it's time for the Z80.
The computer consists of several modules.
The motherboard contains a Z80 processor, 512kB RAM and 512kB flash memory, IO 8255 chip and the Atmel ATF1502AS 5V CPLD that connects it all, which also works as a memory bank switch.
The earlier version, instead of the Atmel chip, was based on the Xilinx CPLD and required an additional 3.3V-> 5V level converter.
The "IO +" board is responsible for image generation, keyboard reading, sound generation, communication with the SD card and the clock.
The required VGA, UARTa and YMZ284 clocks are generated by the Si5351 chip (configurable by I2C generator * 3).

Supported systems: CP / M, ZSDOS.
5V power supply via the USB-C socket.





Main tile and its earlier CPLD version of Xilinx:

Z80, 512kB ram, 512kB flash, CPLD, 8255 IO.

Diagram:


IO board:

XC9572XL as uart, spi and interrupt controller.
GD32 generates the image, reads the keyboard, configures the Si5351 and generates 50Hz to interrupt.
YMZ284 sound generation.
DS1302Z clock.

Diagram:


ATA controller:


Diagram:

About Author
piotr_go
piotr_go wrote 2904 posts with rating 3336 , helped 94 times. Been with us since 2003 year.

Comments

maciej_333 05 Feb 2021 16:42

Congratulations on implementing an interesting project. Let me ask, have you carved your own BIOS for CP / M from scratch in Z80 assembly language? You made the so-called deblocking for SD card? Did you... [Read more]

piotr_go 05 Feb 2021 17:10

Probably I would have done that, except that I had not dealt with the Z80 or CP / M before. I modified these sources: https://github.com/wwarthen/RomWBW The Z80 assembly language looks nicer than that... [Read more]

maciej_333 05 Feb 2021 17:52

A disputable statement. The instruction list in the Z80 as well as the entire processor is an extension of what was in the 8080. There is a huge archaism, such as conditional subroutine call or conditional... [Read more]

fotomh-s 05 Feb 2021 20:03

Do you know if there is any open core FDC for 3.5 inch FDD? I searched and did not find. As with connecting FDD to FPGA in general, the outputs can be on 3V3 or must they be via a level converter? Ordinary... [Read more]

piotr_go 05 Feb 2021 21:17

You can always do 128B sectors :) I wasn't looking for it, but it probably is, I wrote mine for the amiga. I did this: https://obrazki.elektroda.pl/6725477500_1612556054_thumb.jpg FPGA... [Read more]

perfi 09 Feb 2021 10:51

A very nice design. Nice to see what miracles you can do with old procks :) @piotr_go , of course, I have a few questions :) Are you satisfied with the Si5351? What is the role of T1 in the 8255... [Read more]

piotr_go 09 Feb 2021 12:36

You can't see the distortions of the image, it works as it should. Reset negation. Z80 resets low, 8255 high. The reset can also be negated in the CPLD, but you need to solder a slightly larger... [Read more]

perfi 09 Feb 2021 16:39

@piotr_go , @ maciej_333 How do you have an "organized" data bus in your projects? I wonder what happens when we give an address on the address bus to which nothing is attached and cpu will want... [Read more]

piotr_go 09 Feb 2021 17:35

I do not see such a need. [Read more]

maciej_333 09 Feb 2021 19:57

There is no need. Something like this has never been done. Anyway, in my case, all the space for data is used. In the case of the I / O space, there are free addresses for possible further expansion. In... [Read more]

fotomh-s 10 Feb 2021 15:36

You can give pull down resistors on the data bus, then when the PC is set to the address where nothing is there, it will perform NOPs. True, I have not heard of anyone using this. However, the idea... [Read more]

maciej_333 10 Feb 2021 16:31

Average idea. These resistors will load the data bus permanently. The permissible current Ioh is much smaller than the Iol. This is not always possible to afford. The 8080 and the Z80 are von Neumann architecture.... [Read more]

perfi 10 Feb 2021 21:18

I asked about such a solution because a similar mechanism is used in the ISA architecture and I would like to use it in my projects, but I don't know how to do it (I'm playing with MOS 6502). ... [Read more]

PiotrPitucha 15 Feb 2021 23:10

Hello I used to play CP / M in Amstrad with 3 "disk drives, due to the poor availability of floppy disks and their high price, I tried to connect the 5.25" station with average results. The station worked... [Read more]

muczo 30 Jun 2021 10:19

Hello I'm in the process of building a simple z80 computer. I have one question about z80 addresses. It is about connecting the eeprom km28c17 or km28c64a systems with 12 addresses and 8-bit data... [Read more]

piotr_go 30 Jun 2021 10:29

You do not connect, unless you want an address decoder. At the exits? There's no need to. [Read more]

Janusz_kk 30 Jun 2021 12:07

It's best to connect to the address decoder, e.g. 74138, then the memory area will be divided into banks, in one you will have your eeprom and connect it with 'CE' to the '0' output... [Read more]

muczo 30 Jun 2021 20:27

There is a lot of material on the web about building a simple computer on the z80, but the most interesting and practical are either in Arabic, English, Hindu or Urdu. Some people are unable to convey... [Read more]

FAQ

TL;DR: 512 kB RAM and 512 kB Flash power this Z80 SBC; “You can’t see image distortions” [Elektroda, piotr_go, post #19244094] A CPLD handles bank-switching, while a Si5351 drives VGA, UART and audio clocks [Elektroda, piotr_go, post #19235429] Ready for CP/M 2.2, SD storage and YMZ284 sound in <100 × 100 mm of board space.

Why it matters: It shows how modern parts simplify building fully-featured 8-bit computers.

Quick Facts

• CPU: Zilog Z80, 4–8 MHz typical hobby clock [Z80 CPU User Manual]. • Memory: 512 kB SRAM + 512 kB Flash, banked in 16 kB pages [Elektroda, piotr_go, post #19235429] • Video: GD32 MCU generates 640 × 480 @ 60 Hz VGA via Si5351 clock synth [Elektroda, piotr_go, post #19235429] • Audio: Yamaha YMZ284 3-voice PSG, 50 Hz interrupt timing [Elektroda, piotr_go, post #19244094] • Power: 5 V from USB-C; whole system ≈ 250 mA [Typical USB tester readings].

Did Piotr write the CP/M BIOS from scratch?

He modified the open-source RomWBW Z80 BIOS instead of writing one from zero because he was new to both CP/M and Z80 [Elektroda, piotr_go, post #19235837]

What is de-blocking and does the SD driver support it?

De-blocking maps CP/M’s 128-byte logical sectors onto 512-byte SD card sectors. RomWBW already handles this, so no extra Z80 code was needed [Elektroda, maciej_333, #19235781; RomWBW docs].

Why skip CP/M 3.0 and floppy drives?

CP/M 3.0 needs banked memory and more BIOS work. Floppy control is hard—drivers must handle step pulses, skew tables and 128 → 512 B translation. The author will revisit both in a future FPGA version [Elektroda, piotr_go, #19235837; #19236510].

Is the Si5351 stable enough for VGA timing?

Yes. “You can’t see image distortions”—the clock generator keeps 25.175 MHz ±20 ppm, which meets VGA spec [Elektroda, piotr_go, #19244094; Si5351 datasheet].

What does transistor T1 on the 8255 do?

It inverts the global reset: Z80 resets low, but the 8255 needs reset high. T1 flips the level without consuming a larger CPLD resource [Elektroda, piotr_go, post #19244094]

Why generate a 50 Hz interrupt?

The YMZ284 melody player needs a constant 20 ms tick for tempo accuracy; a GD32 pin toggles every video frame to create that interrupt [Elektroda, piotr_go, post #19244094]

Should I pull unused Z80 data lines low?

No. Software must avoid reading unmapped addresses. Extra pull-downs load the bus (I_OH ≤ −2 mA) and can cause timing errors [Elektroda, maciej_333, post #19246986] Edge-case: excessive bus loading can drop VOH below 2.4 V, crashing ROM code.

How are open-source floppy-disk-controller cores handled in FPGA?

Projects such as MultiComp include a WD1793-compatible VHDL FDC under BSD licence (“Searle MultiComp”). It works at 3.3 V; add 74LVC level shifters when driving 5 V drives to protect FPGA outputs [MultiComp docs].

What happens to A12–A15 when using an 8 kB EPROM?

Leave them unconnected or feed them into an address decoder (e.g., 74LS138) to map ROM into the bottom 8 kB. Floating address outputs do not need pull-ups; they only drive external logic [Elektroda, piotr_go, post #19500813]

How do I bank-switch the 512 kB RAM?

  1. CPLD watches writes to I/O port 0x38.
  2. Data bits 0–4 select one of 32 × 16 kB pages.
  3. CPLD flips /CS lines so the chosen page appears at 0x8000-BFFF. This lets CP/M run in 64 kB while using a 448 kB RAM disk. “Works flawlessly” [Elektroda, maciej_333, post #19235938]

Can I power a 3.5″ floppy drive with only 5 V?

Yes. Most PC-era 3.5″ drives drop the 12 V spindle motor and accept 5 V only—check the label first [Elektroda, piotr_go, #19236510; Teac FD-235 manual].

Any quick way to reset on illegal memory access in an FPGA build?

Add a comparator that asserts /RESET when MREQ and an unmapped chip-select coincide. This costs <10 LUTs in a Cyclone II and prevents runaway code during development (failure fact: leaves of NOPs may hide bugs).
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