DIY-A586 v1.9 by piotr_go

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#1 04 May 2022 17:42

Hello
I would like to present the 1.9 DIY-A586 version, with the modifications that have come to my mind over the years. I skipped a few numbers so that I would not be tempted by another v1.x from XC6SLX9 .
Differences: 32MB RAM, JOY1 / 2 without multiplexing, 2 flopps without additional circuits, 18.432MHz generator, space for THT LEDs, 5k1 USB-C pull-downs, various minor fixes.

The board has:
- FPGA Spartan6 XC6SLX9
- 32MB 16bit SDRAM memory
- 16MB flash for core and ROMs
- HDMI output
- analog audio output + tape recorder input
- SD slot
- RS232
- 2 * joystick port
- 2 * PS / 2
- A500 keyboard connector
- floppy disk drive connectors
- 2 buttons (menu and reset)
- 2 LEDs
- 5V USB-C power socket
- dimensions 100x100mm

There are up to 30 configurations in flash that can be loaded into an FPGA.

Link

Mikan core (8MB CHIP, 23.5MB FAST) :

I thought it would fail, but somehow the 8MB DMA CHIP came in.

Diagram and gerberas in the appendix.
Commercial use prohibited.

Attachments:

piotr_go DIY-A586 v1.9.tar.gz Download (1.45 MB) Punkty: 4 for the user

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About Author
piotr_go piotr_go

DIY electronics designer
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Joined: 10 Jan 2003

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piotr_go wrote 2450 posts with rating 2651, helped 88 times. Been with us since 2003 year.
#2

Baskhaal Baskhaal

Level 17

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#2 04 May 2022 20:59

Cool thing! I feel the subject in my free time.
If you want to do a mass show then let me know, I will do and SMT and THT at a good price.
#3

katakrowa katakrowa

Level 22

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#3 05 May 2022 15:12

It's something based on: https://en.wikipedia.org/wiki/Minimig or https://en.wikipedia.org/wiki/MiSTer
Or maybe another approach?
#4

piotr_go piotr_go

DIY electronics designer

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#4 05 May 2022 16:24

Own core.
#5

tronics tronics

Level 38

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#5 05 May 2022 17:22

Softcore CPU and Chipset as I understand it? Is the CPU with any of the existing solutions?
#6

katakrowa katakrowa

Level 22

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#6 05 May 2022 17:36

piotr_go wrote:
Own core.

All including own CPU implementation?
#7

piotr_go piotr_go

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#7 05 May 2022 17:38

TG68, like in core with minimig, all the rest is mine.
If I find time, I will replace it with something of my own.
#8

katakrowa katakrowa

Level 22

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#8 05 May 2022 17:47

piotr_go wrote:
If I find time, I will replace it with my own.

M68000 is not a Z80, however, that in three afternoons you can write your own implementation, but I wish you perseverance and a lot of fun while writing
#9

piotr_go piotr_go

DIY electronics designer

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#9 05 May 2022 17:54

katakrowa wrote:
The M68000 is not the Z80, however, that you can write your own implementation in three afternoons

It is quite simple compared to "playing" with the cycle consistency of the rest of the core.
#10

tronics tronics

Level 38

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#10 05 May 2022 18:01

And how is the compatibility at the moment? Are there any bugs in demos or games, are they all right?
#11

piotr_go piotr_go

DIY electronics designer

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#11 05 May 2022 18:07

As for the games, I deleted what I noticed.
I have not tested the dem.
#12

Macosmail Macosmail

Level 34

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#12 05 May 2022 21:16

A very nice device SysInfo shows only 2 MIPS at 98 MHz? Workbench works quite lively. Screen operations faster than original ECS / AGA chips?
#13

piotr_go piotr_go

DIY electronics designer

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#13 05 May 2022 21:44

Macosmail wrote:
SysInfo shows only 2 MIPS at 98 MHz?

I suspect it's because of the faster memory. In the original DMA takes most of the bandwidth.

Macosmail wrote:
Screen operations faster than original ECS / AGA chips?

I also had such an impression (compared to the bare 1200).
Lotus III runs fairly smoothly.
#14

samowitsch samowitsch

Level 6

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#14 30 May 2022 21:25

Hi Piotr. Is a Winbond W9825G6KH-5 absolutely necessary or can it also be a W9825G6KH-6?
#15

Ondo Ondo

Level 11

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#15 30 May 2022 23:12

Beautiful job, at first glance I thought it was some Virtex, and the Spartan was enough. How many FPGAs does the entire project take?
#16

piotr_go piotr_go

DIY electronics designer

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#16 30 May 2022 23:42

Amiga - 100%
#17

Ondo Ondo

Level 11

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#17 31 May 2022 00:34

100% FPGA resources? With all due respect, you are probably a miracle worker, good projects tailored to specific FPGA blocks reach 60-70% of resources.
#18

piotr_go piotr_go

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#18 31 May 2022 09:38

samowitsch wrote:
Is Winbond W9825G6KH-5 absolutely necessary or can it also be W9825G6KH-6?

It should work, but I haven't tested it.

Ondo wrote:
100% FPGA resources?

Usually it does not fit, depends on the whim of the synthesis.
#19

Ondo Ondo

Level 11

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#19 31 May 2022 14:45

piotr_go wrote:

Ondo wrote:
100% FPGA resources?

Usually it does not fit, depends on the whim of the synthesis.
It's normal to have to trim, but I mean the utilization level of the chip, the ISE spits out a synthesis result showing what percentage of resources are unused due to lack of routing or unused resources (memory, multipliers, DCM etc). It signifies a bit how a design is optimized for a specific FPGA, or how a particular FPGA is good for a specific task.
#20

piotr_go piotr_go

DIY electronics designer

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#20 31 May 2022 15:56

Ondo wrote:
It's normal to cut

Often it is enough to rename a signal or some other nonsensical modification.

Ondo wrote:
I mean the level of utilization of the system

Code: dos
Log in, to see the code
#21

__Grzegorz__ __Grzegorz__

Level 29

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#21 31 May 2022 16:20

Projects in ISE can be stuffed with a "shoe" using "Project" -> "Design Goals and Strategies".
There is an "Area" option which sometimes works wonders.
It spoils the timings a bit, but ... it is :)

It allowed to cram into the SLX9 a project that, after synthesis, had 111% of the resource occupancy :)

You can troubleshoot with
- Synthesis: "Optimization Goal" (changed to Area),
- Mapping: "Combinatorial Logic Optimalization" (enable)
- Mapping: "Global Optimization" set to "Area"
- Mapping: "Allow Logic Optimization Across Hierarchy"
- Mapping: "LUT Combining" to Area
- Mapping: "Maximum compression" - it can take ages unfortunately
- Mapping: "Map Slice Logic into unused BlockRAM" - as long as you have free BLOCKRAM
#22

piotr_go piotr_go

DIY electronics designer

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#22 31 May 2022 19:29

__Grzegorz__ wrote:
There is an "Area" option which sometimes works wonders.

This occupation is after this wonder
#23

samowitsch samowitsch

Level 6

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#23 04 Jun 2022 14:39

piotr_go wrote:

samowitsch wrote:
Is a Winbond W9825G6KH-5 absolutely necessary or can it also be a W9825G6KH-6?

It should work, but I haven't tested it.
#24

piotr_go piotr_go

DIY electronics designer

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#24 04 Jun 2022 22:46

Mouser. I bought a few pcs last year.
#25

mopplayer6 mopplayer6

Level 2

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#25 29 Aug 2022 04:19

Hi piotr_go
I use Lichee Tang Primer to transmit HDMI with audio but packages seem to have some issues. Could you please share how to transfer audio via HDMI to Lichee Tang Primer?
#26

__Grzegorz__ __Grzegorz__

Level 29

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#26 29 Aug 2022 10:00

And also regarding the FPGA occupancy:
instead of the XC6SLX9 I suggest using the EFINIX T20Q144.

I'm just transferring my projects to this chip.
It has ~ 50% more logic, something that I had to stuff into the SLX9, it goes into the T20Q144 without any problems.
Light environment, no simulator, but if you organize modelsim, no problem
Scalak has dedicated LVDS I / O, which are limited when it comes to using them as I / O, and slightly less dedicated clock inputs.

T20Q144 are in digikeyu, in "normal" money.
#27

piotr_go piotr_go

DIY electronics designer

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#27 29 Aug 2022 11:25

@__Grzegorz__
It looks interesting, but not enough IO. In my spare time, I read about him. Is the Linux version soft?
I promised myself that the next version 1.xx will not be created, and versions 2.xx will have a lot of stock, even with AGA + 68020.
At the moment 2.0 is on Cyclone 4 (22320 LEs). Arrow starters are waiting in the queue, with even larger FPGAs, bought in the promotion for pennies.

@ mopplayer6
I'm sending in analog, fewer problems
What's the problem?
#28

__Grzegorz__ __Grzegorz__

Level 29

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#28 29 Aug 2022 11:49

piotr_go wrote:
Is the Linux version soft?

Is.

Quote:
Linux environments:
- Operating system:
- Ubuntu v18.04 or later
- Red Hat Enterprise x86-64 v7.4 or later
- CentOS x86-64 v7.4 or later
#29

mopplayer6 mopplayer6

Level 2

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#29 30 Aug 2022 13:44

Hi @piotr_go
My problem is that the lowest resolution in the HDMI standard is 640x480.
The NES was 512x480, how could I send the packet with audio and HDMI requirement?
I can see your video may work properly, can you please share how to do it?
#30

piotr_go piotr_go

DIY electronics designer

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#30 30 Aug 2022 14:09

I'm guessing at 640x480 you don't have room for audio packets?
Try stopping the NES clock on each line (before or after the image) to make them longer I did just that.
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