Hello I would like to present the 1.9 DIY-A586 version, with the modifications that have come to my mind over the years. I skipped a few numbers so that I would not be tempted by another v1.x from XC6SLX9 . Differences: 32MB RAM, JOY1 / 2 without multiplexing, 2 flopps without additional circuits, 18.432MHz generator, space for THT LEDs, 5k1 USB-C pull-downs, various minor fixes.
The board has: - FPGA Spartan6 XC6SLX9 - 32MB 16bit SDRAM memory - 16MB flash for core and ROMs - HDMI output - analog audio output + tape recorder input - SD slot - RS232 - 2 * joystick port - 2 * PS / 2 - A500 keyboard connector - floppy disk drive connectors - 2 buttons (menu and reset) - 2 LEDs - 5V USB-C power socket - dimensions 100x100mm
There are up to 30 configurations in flash that can be loaded into an FPGA.
Usually it does not fit, depends on the whim of the synthesis.
It's normal to have to trim, but I mean the utilization level of the chip, the ISE spits out a synthesis result showing what percentage of resources are unused due to lack of routing or unused resources (memory, multipliers, DCM etc). It signifies a bit how a design is optimized for a specific FPGA, or how a particular FPGA is good for a specific task.
Projects in ISE can be stuffed with a "shoe" using "Project" -> "Design Goals and Strategies". There is an "Area" option which sometimes works wonders. It spoils the timings a bit, but ... it is :)
It allowed to cram into the SLX9 a project that, after synthesis, had 111% of the resource occupancy :)
You can troubleshoot with - Synthesis: "Optimization Goal" (changed to Area), - Mapping: "Combinatorial Logic Optimalization" (enable) - Mapping: "Global Optimization" set to "Area" - Mapping: "Allow Logic Optimization Across Hierarchy" - Mapping: "LUT Combining" to Area - Mapping: "Maximum compression" - it can take ages unfortunately - Mapping: "Map Slice Logic into unused BlockRAM" - as long as you have free BLOCKRAM
And also regarding the FPGA occupancy: instead of the XC6SLX9 I suggest using the EFINIX T20Q144.
I'm just transferring my projects to this chip. It has ~ 50% more logic, something that I had to stuff into the SLX9, it goes into the T20Q144 without any problems. Light environment, no simulator, but if you organize modelsim, no problem Scalak has dedicated LVDS I / O, which are limited when it comes to using them as I / O, and slightly less dedicated clock inputs.
@__Grzegorz__ It looks interesting, but not enough IO. In my spare time, I read about him. Is the Linux version soft? I promised myself that the next version 1.xx will not be created, and versions 2.xx will have a lot of stock, even with AGA + 68020. At the moment 2.0 is on Cyclone 4 (22320 LEs). Arrow starters are waiting in the queue, with even larger FPGAs, bought in the promotion for pennies.
@ mopplayer6 I'm sending in analog, fewer problems What's the problem?
Hi @piotr_go My problem is that the lowest resolution in the HDMI standard is 640x480. The NES was 512x480, how could I send the packet with audio and HDMI requirement? I can see your video may work properly, can you please share how to do it?