DIY-A586 v1.9 by piotr_go

Hello
I would like to present the 1.9 DIY-A586 version, with the modifications that have come to my mind over the years. I skipped a few numbers so that I would not be tempted by another v1.x from XC6SLX9 .
Differences: 32MB RAM, JOY1 / 2 without multiplexing, 2 flopps without additional circuits, 18.432MHz generator, space for THT LEDs, 5k1 USB-C pull-downs, various minor fixes.

The board has:
- FPGA Spartan6 XC6SLX9
- 32MB 16bit SDRAM memory
- 16MB flash for core and ROMs
- HDMI output
- analog audio output + tape recorder input
- SD slot
- RS232
- 2 * joystick port
- 2 * PS / 2
- A500 keyboard connector
- floppy disk drive connectors
- 2 buttons (menu and reset)
- 2 LEDs
- 5V USB-C power socket
- dimensions 100x100mm



There are up to 30 configurations in flash that can be loaded into an FPGA.





Mikan core (8MB CHIP, 23.5MB FAST) :

I thought it would fail, but somehow the 8MB DMA CHIP came in.

Diagram and gerberas in the appendix.
Commercial use prohibited.

Cool thing! I feel the subject in my free time.
If you want to do a mass show then let me know, I will do and SMT and THT at a good price.

It's something based on: https://en.wikipedia.org/wiki/Minimig or https://en.wikipedia.org/wiki/MiSTer
Or maybe another approach?

Own core.

Softcore CPU and Chipset as I understand it? Is the CPU with any of the existing solutions?

piotr_go wrote:

Own core.

All including own CPU implementation?

TG68, like in core with minimig, all the rest is mine.
If I find time, I will replace it with something of my own.

piotr_go wrote:

If I find time, I will replace it with my own.

M68000 is not a Z80, however, that in three afternoons you can write your own implementation, but I wish you perseverance and a lot of fun while writing

katakrowa wrote:

The M68000 is not the Z80, however, that you can write your own implementation in three afternoons

It is quite simple compared to "playing" with the cycle consistency of the rest of the core.

And how is the compatibility at the moment? Are there any bugs in demos or games, are they all right?

As for the games, I deleted what I noticed.
I have not tested the dem.

A very nice device SysInfo shows only 2 MIPS at 98 MHz? Workbench works quite lively. Screen operations faster than original ECS / AGA chips?

Macosmail wrote:

SysInfo shows only 2 MIPS at 98 MHz?

I suspect it's because of the faster memory. In the original DMA takes most of the bandwidth.

Macosmail wrote:

Screen operations faster than original ECS / AGA chips?

I also had such an impression (compared to the bare 1200).
Lotus III runs fairly smoothly.

Hi Piotr. Is a Winbond W9825G6KH-5 absolutely necessary or can it also be a W9825G6KH-6?

Beautiful job, at first glance I thought it was some Virtex, and the Spartan was enough. How many FPGAs does the entire project take?

Amiga - 100%

100% FPGA resources? With all due respect, you are probably a miracle worker, good projects tailored to specific FPGA blocks reach 60-70% of resources.

samowitsch wrote:

Is Winbond W9825G6KH-5 absolutely necessary or can it also be W9825G6KH-6?

It should work, but I haven't tested it.

Ondo wrote:

100% FPGA resources?

Usually it does not fit, depends on the whim of the synthesis.

piotr_go wrote:

Ondo wrote:

100% FPGA resources?

Usually it does not fit, depends on the whim of the synthesis.

It's normal to have to trim, but I mean the utilization level of the chip, the ISE spits out a synthesis result showing what percentage of resources are unused due to lack of routing or unused resources (memory, multipliers, DCM etc). It signifies a bit how a design is optimized for a specific FPGA, or how a particular FPGA is good for a specific task.

Ondo wrote:

It's normal to cut

Often it is enough to rename a signal or some other nonsensical modification.

Ondo wrote:

I mean the level of utilization of the system

Projects in ISE can be stuffed with a "shoe" using "Project" -> "Design Goals and Strategies".
There is an "Area" option which sometimes works wonders.
It spoils the timings a bit, but ... it is :)

It allowed to cram into the SLX9 a project that, after synthesis, had 111% of the resource occupancy :)

You can troubleshoot with
- Synthesis: "Optimization Goal" (changed to Area),
- Mapping: "Combinatorial Logic Optimalization" (enable)
- Mapping: "Global Optimization" set to "Area"
- Mapping: "Allow Logic Optimization Across Hierarchy"
- Mapping: "LUT Combining" to Area
- Mapping: "Maximum compression" - it can take ages unfortunately
- Mapping: "Map Slice Logic into unused BlockRAM" - as long as you have free BLOCKRAM

__Grzegorz__ wrote:

There is an "Area" option which sometimes works wonders.

This occupation is after this wonder

piotr_go wrote:

samowitsch wrote:

Is a Winbond W9825G6KH-5 absolutely necessary or can it also be a W9825G6KH-6?

It should work, but I haven't tested it.

Hi. Where did you get the memory?
[F]

Mouser. I bought a few pcs last year.