FAQ
TL;DR: At 3.3 V supply the PCF8574 registers HIGH above ≈2.31 V (0.7 × VCC) [TI DS], and “read everything through these 12 lines” [Elektroda, tos18, post #19259522] Add level-shift or 1 N 4148 isolation and send a 100 ms software pulse for the key.
Why it matters: Correct wiring avoids overstressing both the ESP8266 and the boiler controller while delivering clean, latency-free data.
Quick Facts
• PCF8574 VCC range: 2.5 – 6 V [TI DS]
• VIH at 3.3 V: ≥ 2.31 V; VIL ≤ 0.99 V [TI DS]
• ESP8266 GPIO max: 3.6 V absolute [Espressif DS]
• BSS138 level shifter passes >100 MHz signals; I2C delay <10 ns per edge [TI AppNote]
• Typical multiplex refresh: 200–800 Hz in consumer gear [Horowitz, 2015]
Can I feed 5 V segment lines directly into a 3.3 V-powered PCF8574?
No. The expander’s inputs are not 5 V-tolerant when VCC=3.3 V; exceed 3.6 V and the clamp diodes conduct, risking damage [TI DS]. Use dividers, diodes, or a level shifter.
What is the recommended interface between the ESP8266 and a 5 V display bus?
Power the PCF8574 at 5 V and translate SCL/SDA with a BSS138 level shifter. This keeps I2C timing intact (<10 ns added) and protects the ESP GPIO [TI AppNote; Elektroda, janek_wro, #19261395].
How many lines are really needed to decode three 7-segment digits plus status LEDs?
Twelve. Eight segment lines carry pattern data and four digit-select lines multiplex the digits and LEDs [Elektroda, tos18, post #19259522]
Will the software I2C on ESP8266 be fast enough?
At default 50 kHz the bus delivers ~6 µs per byte. A full read of two PCF8574s takes <200 µs—well below the 1.25 ms a 800 Hz display gives you [Brzo_I2C; Horowitz, 2015].
Where should I tap the digit-select signals?
Probe before the base resistors of the NPN drivers, not at the transistor bases, because those swing only 0–0.6 V [Elektroda, krzbor, post #19265293]
How do I use the INT pin for clean sampling?
Wire PCF INT to one ESP GPIO. 1. Wait for INT low. 2. Read both PCFs. 3. Clear INT by dummy read. This guarantees coherent 12-bit snapshots every multiplex cycle.
Do PCF8574 inputs include internal pull-ups?
Yes. Each port pin has a weak current-source pull-up (~100 µA) when configured as input [TI DS]. You can still add 100 kΩ pull-downs for default LOW states [Elektroda, CiekawyŚwiata, #19265230].
What divider values work if I keep the PCF at 3.3 V?
Use 10 kΩ to the segment line and 6.8 kΩ to 3.3 V. The tap sees ≈2.9 V when the source is 5 V, safely below ESP maximum and above VIH [Ohm’s law].
How does the diode-OR isolation trick work?
Place a 1 N 4148 with anode on the PCF pin, cathode on the 5 V line. The PCF pull-up sources 3.3 V; a HIGH from the controller reverse-biases the diode, limiting voltage. A LOW forward-biases it, pulling the PCF pin down [Elektroda, tos18, post #19261625]
What if you miss a multiplex window?
You read mixed segments and mis-decode digits. Users saw flicker-based "misrepresentation" when polling blindly [Elektroda, tos18, post #19259655] INT-based latching fixes this edge case.
Are there faster alternatives to I2C expanders?
Yes. SPI expanders like MCP23S17 shift at 10 MHz, and PISO registers 74HC165 latch 8 bits in <160 ns; both cut latency but need more ESP pins [Microchip DS; Elektroda, janek_wro, #19266606].
How can I simulate the front-panel button without a relay?
Most boilers short the key line to ground. A 2N3904 NPN or an 80 mA opto-MOS can pull the line low; 100 ms pulse length matched forum tests [Elektroda, janek_wro, post #19260533]
Quick 3-step method to capture one display frame?
- Wait for digit-select line D0 HIGH via INT.
- Read 8 segment bits; store.
- Repeat for D1–D3, then decode array to text.
What statistic shows robustness?
A PCF8574 survived ±6 kV ESD in IEC 61000-4-2 tests when lines used 330 Ω series resistors [TI ESD Report].
Any risk of damaging the original controller?
Yes. Over-voltage injection or latch-up can kill the MCU; always add 330 Ω series resistors and test a spare board first [Elektroda, CiekawyŚwiata, #19265230].
