Flash NAND Lite Memory Programmer! TSOP48

Count yourself what nonsense AI writes. 2048*64*2048 = 2Gb and earlier it writes 4Gb.
Tested experimentally and it is supposed to be LUN=2, 2048, 64, 2048+128.

szmichal wrote:

Count yourself what nonsense AI writes. 2048*64*2048 = 2Gb and earlier he writes 4Gb.

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The earlier description referred to the image not the TH58NVG2S3 chip

Write to the manufacturer maybe they will provide documentation but knowing life they will not even write back but it does not hurt to try.

If you set LUN to 1, will it read the memory?

Take a look here, although I don't know how reliable the data they give there is:
https://www.ovaga.com/products/detail/th58nvg2s3htai0

if I set the LUN to 1 and the number of blocks to 4096, which corresponds to 4Gb, it will not read. Lun=1 and B=2048 will read but half of it, i.e. 2Gb.

Added after 19 [minutes]:

Another question, I guess to the author, about the logic behind the programmer and its software. What does this kit actually read from the memory page? It reads the raw content of the USER DATA + SPARE Bytes, is the USER DATA area already polynomially corrected ?

Could the author of the software clear up any doubts about how to read the memory ?
I have never done any project on parallel NAND but I have done on serial, the difference is probably only in the interface.
It would be great if there was a possibility to set in the software whether we read the "raw" memory and its "spare bytes" or whether we read the data already corrected by the ECC mechanism of the memory itself. Either method has its uses for other purposes.

The NANDLite programmer reads the raw data, and does not include polynomial correction due to the different algorithms and byte locations that are taken for calculations.

"Reads raw USER DATA + SPARE Bytes".

And isn't it enough to enable correction in memory and then you read from the user area data already polynomially corrected according to the memory algorithm ? This is the case in serial.

Not enough, because the memory MUST have ECC support. and unfortunately most common NAND memory does not have ECC support, so you have to do your own (processor) counting.

Examples of memory with ECC are BeNAND

Sure. It's just that my whole notion of NAND was based on this one project I did and assumed equivalence between the types. Thanks for the clarification.

LUN introduced such a concept MICRON and in general it is of little relevance in most cases as long as the addressing of the parties is uniform.

In the case of TOSHIBA they did a little bit of work and it turns out that in some memories the addressing is discontinuous, i.e. page numbers in a block are addressed, for example, 0..85, then it is necessary to issue a command to change the page set and again address 0..85 and there are, for example, 3 such sets.

It is just a puzzle how to unify this .

I don't remember if it was the same with blocks, i.e. we address blocks sequentially, let's assume from 0..4200.
To address the next one you have to select the next LUN and again address 0..4200.
And we have a discontinuous address space.

We will worry about this in the new version of the programmer.

Added after 20 [minutes]: .

Ok, found:

TC58NVG6T2FTA00

That is, 64Gbit, in the middle each block has numbered pages 0..85
then changing the set of pages and again numbering 0..85 of the same block

In total each block has 258 pages of 9216 bytes.

There are 4156 blocks.

I encourage you to read for curiosity .

Hi author, used to be looking for K9GAG08U0E chips for testing , I have collected some and can share for covering postage. If current please contact me on @. Regards

Author, please help. How should these chips be connected? I'm newbie, and in college I was assigned to do a project in the form of this programmer

You have a diagram at the beginning of the topic, something here I still have to help you with?